1. Field of the Invention
The present invention relates generally to address distribution in a high speed memory macro, and more particularly, to a method of time reduction and energy conservation during address distribution in a high speed memory macro.
2. Description of the Related Art
High speed macros are used to realize high-performance operation of data processing systems and network designs. Specifically, high speed memory macros are used to distribute signals that can be stored as addresses. There is a constant search to decrease the time delay involved with distributing these address signals and to reduce the power involved with operating these macros. A high speed memory macro that distributes signals faster and with less power will be superior.
Traditionally, in memory design one set of address latches is used to store information inside a high speed memory macro. The address latches are placed in the center of the macro and are surrounded by subarrays. The address latches use an address distribution bus to distribute the address signal to the correct subarray and a final decoder to fully decode the specific address signal. Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional high speed memory macro.
As shown in FIG. 1, the address latches 106 are located in the middle of the macro and are surrounded by the subarrays 102, 104, 108 and 110. The subarrays 102 and 104 make up the upper subarray 124 and the subarrays 108 and 110 make up the lower subarray 126. As a signal leaves the address latches it travels through the address distribution bus 120 or 122. These address distribution buses direct the signal to the correct position in the subarrays. Address distribution bus 120 will be used to distribute an address signal to the lower subarray 126, and address distribution bus 122 will be used to distribute an address signal to the upper subarray 124. The address distribution bus distributes the address signal to the correct subarray, but before reaching the subarray the signal will pass through a final decoder 112, 114, 116, or 118. This final decoder is used to fully decode the signal before it is stored in the correct subarray. Accordingly, final decoder 118 will decode a signal that is destined for subarray 102.
According to FIG. 1, an address signal destined for the upper subarray must travel up the address distribution bus 122 to the final decoder 116 or 118 and into the correct subarray 104 or 102, respectively. The problem with this design is that the address signals need to travel half of the length of a memory array height. This memory array height is determined by the number of entries in the array and the actual cell height. A shorter wire length will allow the signal to be distributed faster and with greater precision. Any extra wire length will affect the distribution delay, skew, and slope of the signal.
Referring to FIG. 2 of the drawings, reference numeral 200 generally designates a block diagram illustrating address signal distribution in a high speed memory macro. After a signal enables the address latch 202, the address signal 222 will be distributed by this latch 202 through a communication channel 212. This signal that enables the address latch 202 is produced by a global clock signal. Through the latch 202 this address signal 222 will be destined for the upper subarray 218 or the lower subarray 220. The communication channel 212 will then distribute this signal to a full decoder 204 or 206. Full decoder 204 will be used for the upper subarray 218 and full decoder 206 will be used for the lower subarray 220. After the signal is decoded a communication channel 214 or 216 will direct the signal to a driver 208 or 210, respectively. The driver 208 or 210 will then distribute the decoded signal to the upper subarray 218 or the lower subarray 220. Accordingly, driver 208 is used for an address signal that will be stored in the upper subarray 218 and driver 210 is used for an address signal that will be stored in the lower subarray 220.
One drawback of this design is that the address latches have to be powered on every time that a signal is destined for the upper subarray or the lower subarray. As FIG. 2 depicts, the latch 202 is powered up every time a signal is distributed. Therefore, there is a need for a method and/or apparatus to modify conventional high speed memory macros that address at least some of the problems associated with conventional high speed memory macros.